The present invention relates to reference voltage generating circuits in semiconductor devices, and more particularly to a reference voltage generating circuit in which a reference voltage is produced by converting a voltage level from an external power source and in which a start-up circuit initiates operation of a reference voltage generator when external power is applied.
Recent CMOS semiconductor devices have been manufactured with ultra high density in accordance with sub-micron design rules.
While the size of semiconductor devices is being reduced according to manufacturing technology developments, 5 volts of DC power still is used most commonly for operation of the semiconductor devices. The 5 volts of power sometimes causes hot carrier problems in high density devices, resulting in lower reliability. In order to solve the hot carrier problems, the voltage level of the external power source needs to be reduced to a lower level in order to generate the internal power used to operate the devices. With this solution, reduction of power consumption also will be achieved.
FIG. 1 illustrates a circuit for generating an internal reference voltage. As illustrated in FIG. 1, circuit 1 includes two PMOS transistors, MP0 and MP1, two NMOS transistors, MN0 and MN1, and resistor R1. This circuit has two operating states. One state is that of normal operation in which a reference voltage is generated, and the other state is one in which a reference voltage is not generated, because the current between the source and drain of the NMOS and PMOS transistors is nearly zero amperes.
Particularly during the initial stage of power application from the power supply, since the MOS transistors start their operation with zero current and voltage, sometimes the transistors do not arrive at a normal operation state without means to assist their operation. Thus, this circuit does not start up independently.
In order to solve this problem of non-self-start-up, the circuit for generating a reference voltage has to include a start-up circuit so that all MOS transistors reach a normal operation state, such as are illustrated in FIG. 2 and FIG. 3.
An improved circuit for generating a reference voltage illustrated in FIG. 2 comprises reference voltage generator 1, which includes MOS transistors MP0, MP1, MN0 and MN1 and resistor R1, and start-up circuit 2, which includes a number of PMOS transistors MPS.sub.0 -MPS.sub.m-1, and also transistor MPSm. In the start-up circuit, PMOS transistors MPS.sub.0 -MPS.sub.m-1 are connected in series between Vcc and Vss, and the gates are connected to a source of an adjacent PMOS transistor like a diode as illustrated. The source of MOS transistor MPSm is connected to the gate of PMOS transistor MP0, the gate of transistor MPSm to the gate of transistor MPS1, and the drain of transistor MPSm to Vss.
In FIG. 2, the voltage level of the source of transistor MPSm is equal to Vcc-Vth because it is connected to the gate of transistor MP0. The gate voltage of MOS transistor MPSm in start-up circuit 2, which is connected to the gate of PMOS transistor MPS1, is equal to Vcc-2Vth.
Here, in order to make the same Vth of in-series-connected PMOS transistors MPSo-MPSm-1 between power source Vcc and ground Vss, the bulk of the PMOS transistors are connected to their respective sources. The source voltage of PMOS transistor MPSm becomes Vcc-Vth, and the gate voltage of transistor MPSm becomes Vcc-2Vth. Accordingly, the voltage difference between the gate and the source of transistor MPSm maintains Vth, so that a certain amount of current flows from transistor MP0 to transistor MPSm, so that transistors MP0, MP1, MN0 and MN1 are turned-on in sequence. Thus, the circuit for generating a reference voltage operates in normal operation with transistors MP0 and MP1 turned-on.
As can be seen in FIG. 2, however, a plurality of transistors are connected in series between Vcc and Vss, and thus current flows through them, resulting in power consumption during normal operation, which is not desirable for low power operation.
In order to avoid such power consumption, a reference voltage generating circuit has been provided as illustrated in FIG. 3. This circuit was disclosed in U.S. Pat. No. 5,243,231. This circuit comprises reference voltage generator 1, and start-up circuit 3 consisting of resistor R2 and capacitor Co connected in series between power source Vcc and reference voltage terminal Vref. Reference voltage generator 1 generates a reference voltage and start-up circuit 3 generates a start-up current when the external voltage is applied to the Vcc and Vss nodes. In the circuit of FIG. 3, the structure of reference voltage generator 1 is similar to that of FIG. 1. In start-up circuit 3, resistor R2 and capacitor Co are connected in series between power source Vcc and reference voltage output Vref. If the Vcc voltage is increased, the voltage of node N1 and node Vref also are increased by a coupling effect with the Vcc node. If the reference voltage exceeds the threshold voltage of NMOS transistor MN1, transistor MN1 is turned on and transistor MP1 is turned on by the current drawn by transistor MN1 (I.sub.2). The turning on of transistor MP1 causes current (I.sub.1) to flow through transistor MPO, which in turn turns on transistor MN0. The current is controlled by resistor R1. That is, turned-on transistors MN1 and MP1 cause transistors MP0 and MN0 to start-up, so that the reference voltage generator operates normally. The reference voltage generator produces a reference voltage with a constant level, when the voltage level of Vcc is no longer increasing, with bias current I.sub.i held at a desired level and mirror current I.sub.2 maintaining the same current as I.sub.1, a constant reference voltage is output regardless of the Vcc level. If the reference voltage reaches a certain level, the coupling effect of capacitor Co is negligible, and thus the reference voltage generator operates normally.
This circuit has a disadvantage in that R-C coupling with Vcc may cause variation of the reference voltage when Vcc is very noisy. The reference voltage of this circuit may fluctuate when the Vcc level is changed during a voltage bump period or by external noise.